The present invention relates generally to liquid crystal displays (LCDs) and specifically to active matrix liquid crystal displays (AMLCDs), and to AMLCD's having integrated row and column drivers.
Presently, AMLCDs are being developed and used for a wide variety of flat panel display and projection light valve display applications. Flat panel AMLCDs are of interest for a number of commercial, industrial, military and space applications because of their potential for reduced weight, volume and power consumption, and enhanced resolution and reliability compared to the conventional CRT displays. Similarly, light valve AMLCDs are of interest for a variety of helmet and head mounted displays and large area projection displays because of their potential for compactness, high resolution, high brightness and low power. Generally, either amorphous silicon (a-Si) or polysilicon (poly-Si) thin film transistor (TFT) technologies are used in the fabrication of the prior art AMLCDs. An a-Si TFT has a low mobility (approximately 1 Cm.sup.2 /V. Sec.) and hence does not allow fabrication of integrated row and column drivers for the AMLCDs. Poly-Si TFTs result in a lower pixel aperture ratio, and display performance degradation due to higher threshold voltage, higher leakage currents and high defect densities. One of the important factors influencing the power requirement of the AMLCDs is the pixel aperture ratio. When the pixel aperture ratio is small, it requires the use of a brighter backlight which consumes more power for achieving a display with a given brightness. For many applications, particularly portable devices such as displays for notebook computers, minimizing the power consumption is very important. Unfortunately, the present high resolution AMLCD pixel designs result in a very low aperture ratio, in the typical range of 30-35%.
Single silicon (SC-Si) transistors, due to their high mobility (electron mobility approximately 600 Cm.sup.2 /V. Sec.), 0 low threshold voltage and low leakage currents offer several advantages for the AMLCDs. SC-Si allows fabrication of CMOS integrated drivers required for high resolution displays using a simple architecture, resulting in much fewer external interconnects between the integrated drivers and the display controller, thus achieving a compact and high reliability display.
However, conventional active matrix pixel/transistor designs using SC-Si results in reduced operating voltage capacity due to "voltage snapback" as a result of the floating body and the parasitic bipolar transistor operation. The body region of metal-oxide semiconductor (MOS) circuits on silicon on insulator (SOI) substrates is typically floating. SOI MOSFETs with a floating body exhibit a kink, or increase in drain current, in the saturation region of the I.sub.D vs. V.sub.DS characteristic due to a reduction of the MOSFET threshold voltage which occurs when the majority carriers, generated at the drain by impact ionization, forward bias the body to source junction. A sufficiently high body to source forward bias can cause a rapid increase in drain current and result in premature drain to source breakdown, causing the transistor to latch up. The voltage at which this occurs is referred to as the snapback voltage. P-channel SOI devices are generally free of kink effect, and the breakdown voltage problems because the coefficient of electron-hole pairs generation by the energetic holes is much lower and the minority carrier (hole) lifetime is much shorter compared to the NMOS devices. As a result, body tie is not generally important for PMOS devices.
While there are some benefits to using SC-Si TFTs in AMLCDs using conventional designs when compared to using polysilicon TFTs, one drawback is that the display operating voltage is limited by the snapback voltage of the NMOS transistor. This snapback voltage is typically 7 volts or less. Floating body effects can be alleviated by keeping the body region at a fixed potential. A body contact or body tie to an SOI MOSFET has to be formed on the same dielectrically isolated island and isolated from the drain region by a reversed bias junction. For an efficient AMLCD design, it is desirable tc have a display operating voltage (snapback voltage) of at least 10V, and preferably 15V.
In addition, it is desirable to achieve a high aperture ratio in the AMLCD. This aperture ratio is influenced by the TFT and the body tie design.
Another problem with the conventional pixel TFT design is the method used to suppress the problems due to the semiconductor (SC-Si) photoconductivity. Incident light creates electron-hole pairs in the channel region of the transistor. If the body of the transistor is left floating, the electron-hole pairs diffuse to the source and drain regions, and manifest as photocurrents. In the conventional design, an opaque light shield, typically a metal or black pigment layer, is fabricated on top of the TFT. This makes the process more complex and increases cost.
Furthermore, high resolution displays designed for high performance, e.g., many gray levels and broad temperature operation, require a pixel storage capacitor for enhanced display operating margin. Fabrication of the pixel storage capacitor buss makes the processing more complex and increases cost.
Thus, a need exists for AMLCD pixel and transistor design that provide a high snapback voltage, high pixel aperture ratio, reduced photoconductivity problems, simplified pixel storage capacitor function and simplified processing that is compatible with conventional high temperature CMOS IC processes and provides a body contact or tie for the SOI transistor.